1. Technical Field
The invention relates to a resistive memory apparatus. Particularly, the invention relates to a configuration structure of memory cells of a resistive memory apparatus.
2. Related Art
Referring to FIG. 1, FIG. 1 is a circuit diagram of a conventional resistive memory apparatus. The resistive memory apparatus 100 is composed of a plurality of memory cell pairs 111-114. Taking the memory cell pair 111 as an example, the memory cell pair 111 has two memory cells 1111 and 1112, where the memory cell 1111 is constructed by a transistor T1 and a resistor R1, and the memory cell 1112 is constructed by a transistor T2 and a resistor R2.
Regarding to the conventional memory cell pairs 111-114 in FIG. 1, the memory cells in each of the memory cell pairs share a source line and a bit line. Taking the memory cell pair 111 as an example, the memory cells 1111 and 1112 in the memory cell pair 111 share the same bit line BL1 and the same source line SL1. Under the configuration of FIG. 1, the memory cell pairs 111, 113 of the same column share the same source line SL1, and the memory cell pairs 112, 114 of the same column share the same source line SL2; the memory cell pairs 111, 112 of the same row share the same bit line BL1, and the memory cell pairs 113, 114 of the same row share the same bit line BL2.
When a forming operation is performed on the resistive memory apparatus 100, if the memory cell 1111 is a selected memory cell, a word line WL1 corresponding to the memory cell 1111 is set to 3V, and other word lines WL2-WL4 are set to 0V; the bit line BL1 corresponding to the memory cell 1111 is set to 4V, and the bit line BL2 is set to 1.5V; the source line SL1 corresponding to the memory cell 1111 is set to 0V, and the source line SL2 is set to 3V. Now, nodes between the source line SL1 and the bit line BL1 coupled to the memory cells 1111 and 1112 both bear a voltage difference of 4V. Namely, the unselected memory cell 1112 is interfered by the forming operation to cause an unexpected state. Moreover, during a setting operation or a resetting operation of the resistive memory apparatus 100, the similar interferences are also occurred, which may decrease a working performance of the resistive memory apparatus 100.